1. Technical Field
The present invention relates to a memory device and method implementing wordline redundancy without an access time penalty.
2. Prior Art
The application of wordline redundancy to enhance the yield for memory arrays is an accepted fact throughout the semiconductor industry. To be attractive, wordline redundancy should occur without major impact to chip performance (e.g. access time), power requirements or size. Numerous approaches have been proposed with varying degrees of success; for example:
U.S. Pat. No. 4,365,319, issued to Takemae on Dec. 21, 1982, implements redundancy by utilizing two kinds of decoders and drivers, i.e., a PROM decoder for determining whether an incoming address is a defective address, a redundancy driver for driving a redundancy array, and row address decoders and drivers for driving a main memory cell matrix. A first embodiment of the Takemae teachings (FIG. 1) is disadvantageous in that the switch 7 results in an access time penalty, and results in a semiconductor space penalty because the switch must be large to handle high currents. In a second embodiment (FIGS. 2-4), multiple AND gates D.sub.0 -D.sub.63 replace the large switch 7 (FIG. however, this is not much of an improvement because the memory device still suffers from both an access time (i.e., an AND-gate) penalty, and also a semiconductor space penalty as the collective area of the AND gates D.sub.0 -D.sub.63 is still large. A third embodiment (FIGS. 5-10) suffers an access time penalty due to AND-gate delays introduced by the incorporation of AND gates D.sub.91 -D.sub.94 (FIG. 6) and AND gates D.sub.0 -D.sub.3 (FIG. 8A) to control the activation of the decoders and drivers 9 and 10, respectively.
U.S. Pat. No. 3,753,244, issued to Sumilas et al on Aug. 14, 1973 implements redundancy by placing an extra line of memory cells on a memory chip together with a defective address store and a comparator circuit for disabling a defective line of cells and replacing it with the extra line of cells.
The Intel 2164A 64K DRAM represents a memory device where access time is the same whether it is the normal wordlines or the redundancy wordlines which are being used; however, this product is always affected by an access time penalty, whether repaired with wordline redundancy or not, because chip timing is set up to allow for redundancy repairs. More specifically, chip performance is slowed dee to the need to deselect a faulty wordline's word decoder after the redundant word decoders sense a match with an incoming address. Once the match is sensed, a deselect generator is fired, triggered or selected to deselect the entire row of normal word decoders. After the faulty wordline word decoder is deselected, then the wordline drive is enabled. Further discussions concerning the 2164A can be seen in the Intel Application Description AP-131, pp. 14-16, and "An Analysis of the i2164A", Mosaid Incorporated, p. 5, 41-52, April 1982. In addition, it should be further noted that IBM has a 72k DRAM which utilizes a similar approach.
The Bell Lab 64K DRAM (described by R. T. Smith, J .D. Chlipala, J. F. M. Bindels, R. G. Nelson, F. H. Fischer and T. F. Mantz, in "Laser Programmable Redundancy and Yield Improvement in a 64K DRAM", IEEE Journal of Solid-State Circuits, Vol, SC-16, No. 5, pp. 506-514, October 1981), and the 256K DRAM (described by C .A. Benevit, J. M. Cassard, K. J. Dimmler, A. C. Dumbri, M. G. Mound, F. J. Procyk, W. R. Rosenzweig and A. W. Yanof, in "A 256k Dynamic Random Access Memory", IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, pp. 857-861, October 1982), implement wordline redundancy without an access time impact by using laser-fused redundancy on the wordline pitch. No access time penalty is incurred because the defective wordline is permanently disconnected by exploding a programmable link in the wordline. This method of redundancy is disadvantageous because the tighter design rules of present and future high density memory products are causing a shrinkage in the wordline pitch. The result is a requirement for a laser spot size and laser beam position accuracy beyond what is available from laser programming systems today. Thus, laser-fused redundancy is disadvantageous in that the current level of laser technology requires an off wordline pitch method or an increase in memory chip size due to the need for an increased wordline pitch.
The IBM 32K DRAM (described by B. F. Fitzgerald and E. P. Thoma, in "Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement", IBM Journal of Research and Development, Vol. 24, No. 3, pp. 291-295, May 1980) implements wordline redundancy without an access time penalty by adding separate sense amplifier columns for the redundant wordlines. No access penalty is incurred because the redundant wordline and the defective wordline operate in parallel, and the selection of the redundant, versus the normal sense amplifiers, occurs during the sensing operation. This approach is disadvantageous in that chip size is significantly increased due to the need for additional latches for each bitline along the redundant wordline.
Similarly, R. P. Cenker, D. G. Clemons, W. R. Huber, J. B. Petrizzi, F. J. Procyk and G. M. Trout, in "A Fault-Tolerant 64K Dynamic Random Access Memory", IEEE Transactions on Electron Devices, Vol. ED-26, No. 6, June 1979, pp. 853-860, teach a word redundancy technique having no access time penalty, but requiring that disabling fuses be placed within each redundant and non-redundant decoder, thus significantly increasing the required chip area.
B. F. Fitzgerald and D. W. Kemerer, in "Memory System With High-Performance Word Redundancy", IBM Technical Disclosure Bulletin, Vol. 19, No. 5, October 1976, pp. 1638-1639, describe an implementation of word redundancy with no access penalty by accessing both a normal and redundant row in independent arrays. Selection of good data was made at the data out buffers.
While the above approaches represent important advances in semiconductor manufacturing technology, there still exists a need for a memory device and approach which are able to provide wordline redundancy without the disadvantages cited above, i.e., without any access time penalty, and without any significant impact on chip size and power requirements.